final case class TDelay(rate: MaybeRate, trig: GE, dur: GE = 0.1f) extends SingleOut with Product with Serializable
A delay UGen for trigger signals. Other than a normal buffer delay, any new trigger arriving in the time between the previous trigger and the passing of the delay time is ignored.
- trig
The input trigger. A trigger is recognized when the signal passes from non-positive to positive. Note that, no matter what the amplitude of the input trigger is, the UGen will output a delayed trigger of amplitude 1.0.
- dur
The delay time in seconds.
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TDelay(rate: MaybeRate, trig: GE, dur: GE = 0.1f)
- trig
The input trigger. A trigger is recognized when the signal passes from non-positive to positive. Note that, no matter what the amplitude of the input trigger is, the UGen will output a delayed trigger of amplitude 1.0.
- dur
The delay time in seconds.
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- val dur: GE
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def
makeUGen(_args: Vec[UGenIn]): UGenInLike
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Abstract method which must be implemented by creating the actual
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- val rate: MaybeRate
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- val trig: GE
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